1. Field of the Invention
The invention relates to parallel-access memories. It relates more particularly to electrically erasable and programmable non-volatile memories (better known as EEPROMs) although it can be applied to other types of volatile or non-volatile memories.
2. Discussion of the Related Art
Current development of integrated circuit memories with very high information storage capacities (in the sense of the number of information elements stored) has been accompanied by a desire to increase the clock signal frequencies driving the operation of the system in which these memories are used. Thus, there is also a desire for increasingly shorter times of access to the contents of the words contained in these memories. The term "word" in this specification refers to a physical entity whose contents represent a binary information element encoded on B bits, B being an integer. Typically, these words will be formed by B elementary storage cells, each elementary cell of which includes a storage circuit.
From the viewpoint of access time, parallel-access memories have many advantages. In these memories, the addresses of the words to be read and/or written are given on a parallel address bus and the words read and/or written are given and/or received on a parallel data bus. However, the space requirement and the package weight of these memories is often greater than in the case of serial-access memories, because they often use a larger number of connection pins and are therefore costlier.
It is increasingly being sought to raise the operating frequencies of computer systems and hence o of the memories implemented in these systems. In practice, increasing the operating frequencies of memories raises technical problems related to the time of read mode access to the contents of the memories. The term "time of read mode access" is understood to mean the period of time between the time when the address of a word is known to a memory and the time when the binary information element represented by the contents of the cells of the word is available outside the memory.
In practice, the access time is typically limited by the time needed for the sequencing of the following two steps:
(1) the decoding of the address received by the memory, namely the position of various switching devices that connect one or more read circuits to the word whose contents represent the binary information element to be read; and PA1 (2) the reading process proper, namely the extraction of the binary information element, in the form of logic signals, on the basis of the word read (the cells of the word no longer necessarily store a directly usable logic information element but more generally have a variable physical characteristic that an appropriate circuit will convert into a logic signal).
The reduction of the access time entails an increase in the switching speeds during the decoding and/or a reduction of the reaction times of the read circuits. It is often the case that a solution causes high power consumption. This is not desirable for memories that are designed for battery-powered portable applications wherein a minimum power consumption is sought. In practice, it is therefore the maximum admissible access time envisaged that determines the operating frequencies of the systems in which the memories are used.